1. Field of the Invention
The present invention relates to a semiconductor wafer that has a chip region and an evaluation element region and to a semiconductor chip individually separated from the semiconductor wafer. Further, the present invention relates to a method of manufacturing a semiconductor chip from a semiconductor wafer that has a chip region and an evaluation element region.
2. Description of Related Art
Conventionally, in the manufacture of semiconductor chips, evaluation elements known as a Test Element Group (TEG) are disposed between chip regions of a semiconductor wafer (on scribe lines), and the characteristics of the evaluation elements are observed prior to performing separation of individual semiconductor chips. It is known that by observing the characteristics of the TEG, which was formed by an identical process to the process for forming semiconductor chips, a similar effect can be obtained to observing the characteristics of semiconductor chip elements themselves.
In recent years, the prevailing direction of technological development has aimed at reducing the width of the scribe line in order that a larger number of semiconductor chips can be obtained from a single semiconductor wafer. As with the invention disclosed in Japanese Patent Application (JP-A) No. 07-302773, this involves severing, by dicing, an electrode pad used for evaluation element measurement. As disclosed in JP-A No. 2003-234312, when a soft material such as aluminum is used as the material of the electrode pad for evaluation element measurement, burrs (metal peeling) are generated by dicing. When semiconductor devices or semiconductor chips are packaged by Tape Automated Bonding (TAB) techniques such as Tape Carrier Package (TCP) or Chip Size Package (CSP) techniques, or Chip on Glass (COG) techniques that directly mount semiconductor chips onto a glass substrate, there is a risk that adjacent inner leads or wiring will short-circuit due to the burrs (metal peeling). Further to JP-A No. 2003-234312, the invention of JP-A No. 2004-140157 is another example of an invention that addresses this kind of problem.
However, in recent years, despite the fact that TEG electrode pads have also come to be arranged in multiple layers, respective wiring layers have become extremely thin. In the midst of these trends in technological development, the inventors of the present application noticed that the occurrence of burrs (metal peeling) could not be effectively reduced even by using techniques such as those disclosed in the above patent documents. Further, even if a certain degree of reduction is achieved, inner leads and wiring adjacent to burrs (metal peeling) that do occur are not prevented from short-circuiting. The present invention was completed in view of the foregoing circumstances and provides a semiconductor wafer that enables effective reduction in the occurrence of burrs (metal peeling) and in the event, for example, that burrs (metal peeling) do occur, enables reduction in the probability of short-circuiting of adjacent inner leads and wiring and, consequently, that enables production of a large number of high quality semiconductor chips from a single semiconductor wafer.